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altera corporation 2?1 august 2005 2. enhanced configuration devices (epc4, epc8 & epc16) data sheet features enhanced configuration devices include epc4, epc8, and epc16 devices single-chip configuratio n solution for stratix ? series, cyclone? series, apex? ii, apex 20k (including apex 20k, apex 20kc, and apex 20ke), mercury?, acex ? 1k, and flex ? 10k (flex 10ke and flex 10ka) devices contains 4-, 8-, and 16-mbit flash memories for configuration data storage on-chip decompression feature almost doubles the effective configuration density standard flash die and a controller die combined into single stacked chip package external flash interface supports pa rallel programming of flash and external processor access to unused portions of memory flash memory block/sector prote ction capability via external flash interface supported in epc16 and epc4 devices page mode support for remote and local reconfiguration with up to eight configurations for the entire system compatible with stratix series remote system configuration feature supports byte-wide configuration mode fast passive parallel (fpp); 8-bit data output per dclk cycle supports true n-bit concurrent config uration (n = 1, 2, 4, and 8) of altera fpgas pin-selectable 2-ms or 100-ms power-on reset (por) time configuration clock supports pr ogrammable input source and frequency synthesis multiple configuration clock sources supported (internal oscillator and extern al clock input pin) external clock source with frequencies up to 133 mhz internal oscillator de faults to 10 mhz; prog rammable for higher frequencies of 33, 50, and 66 mhz clock synthesis supported via user programmable divide counter available in the 100-pin plastic quad flat pack (pqfp) and the 88-pin ultra fineline bga ? packages vertical migration between all devices supported in the 100-pin pqfp package supply voltage of 3.3 v (core and i/o) cf52002-2.1
2?2 altera corporation configuration handbook, volume 2 august 2005 functional description hardware compliant with ieee std. 1532 in-system programmability (isp) specification supports isp via jam standard te st and programming language (stapl) supports joint test action group (jtag) boundary scan ninit_conf pin allows private jtag instruction to initiate fpga configuration internal pull-up resistor on ninit_conf always enabled user programmable weak internal pull-up resistors on ncs and oe pins internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines standby mode with reduced power consumption f for more information on fpga co nfiguration scheme s and advanced features, refer to the appropriate fpga family chapter in the configuration handbook . functional description the altera enhanced conf iguration device is a single-device, high-speed, advanced configuration solution for very high-density fpgas. the core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash me mory. the flash memory is used to store configuration data for systems made up of one or more altera fpgas. unused portions of the flash memory can be used to store processor code or data that can be ac cessed via the external flash interface after fpga configuration is complete. 1 the external flash interface is currently supported in the epc16 and epc4 devices. for information on using this feature in the epc8 device, contact altera applications. the enhanced configuration device ha s a 3.3-v core and i/o interface. the controller chip is a synchronous system that implements the various interfaces and features. figure 2?1 shows a block diagram of the enhanced configuration device. the controller chip features three separate interfaces: a configuration interface between the controller and the altera fpga(s) a jtag interface on the controller that enables in-system programmability (isp) of the flash memory an external flash interface that the controller shares with an external processor, or fpga implementing a nios ? embedded processor (interface available afte r isp and configuration)
altera corporation 2?3 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet figure 2?1. enhanced configurati on device block diagram the enhanced configuration device features multiple configuration schemes. in addition to supporting the traditional passive serial (ps) configuration scheme for a single device or a serial device chain, the enhanced configuration device features concur rent configuration and parallel configuration. with the co ncurrent configuration scheme, up to eight ps device chains can be configured simultaneously. in the fpp configuration scheme, 8-bits of data are clocked into the fpga each cycle. these schemes offer significantly reduced configuration times over traditional schemes. furthermore, the enhanced configur ation device features a dynamic configuration or page mode feature. this feature allows you to dynamically reconfigure all the fpgas in your system with new images stored in the configuration memo ry. up to eight different system configurations or pages can be stored in memory and selected using the pgm[2..0] pins. your system can be dynamically reconfigured by selecting one of the eight pages and initiating a reconfiguration cycle. this page mode feature combined with the external flash interface allows remote and local updates of system configuration data. the enhanced configuration devices are compatible with the stratix remote system configuration feature. flash fpga controller jtag/isp interface enhanced configuration device shared flash interface shared flash interface
2?4 altera corporation configuration handbook, volume 2 august 2005 functional description 1 for more information on stratix remote system configuration, refer to the using remote system conf iguration with stratix & stratix gx devices chap ter of the stratix device handbook . other user programmable features include: real-time decompression of configuration data programmable configuration clock ( dclk ) flash isp programmable power-on-reset delay ( porsel ) fpga configuration fpga configuration is managed by the configuration controller chip. this process includes reading config uration data from the flash memory, decompressing it if necessary, transm itting configuration data via the appropriate data[] pins, and handling errors conditions. after por, the controller determines the user-defined configuration options by reading its op tion bits from the flas h memory. these options include the configuration scheme, configuration clock speed, decompression, and configuration pa ge settings. the option bits are stored at flash address location 0x8000 (word address) and occupy 512-bits or 32-words of memory. thes e options bits are read using the internal flash interface and the de fault 10 mhz internal oscillator. after obtaining the configuration settin gs, it checks if the fpga is ready to accept configuration data by monitoring the nstatus and conf_done lines. when the fpga is ready ( nstatus is high and conf_done is low), the controller begins data transfer using the dclk and data[] output pins. the controller selects the configuration page to be transmitted to the fp ga(s) by sampling its pgm[2..0] pins after por or reset. the function of the configuration unit is to transmit decompressed data to the fpga, depending on the co nfiguration scheme. the enhanced configuration device supports four co ncurrent configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent per dclk cycle on the data[n] lines). the value n=1 corresponds to the traditional ps configuration scheme. the values n=2, 4, and 8 correspond to concurrent configuration of 2, 4, or 8 different ps configuration chains, respectively. additionally, the fpga can be configured in fpp mode, where eight bits of data are clocked into the fpga per dclk cycle. depending on the configuration bus width (n), the circuit shifts uncompressed configuration data to the valid data[n] pins. unused data[] pins drive low.
altera corporation 2?5 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet in addition to transmitting config uration data to the fpgas, the configuration circuit is also responsible for pausing configuration whenever there is insufficient data av ailable for transmis sion. this occurs when the flash read bandwidth is lower than the configuration write bandwidth. configuration is paused by stopping the dclk to the fpga, when waiting for data to be read from the flash or for data to be decompressed. this techni que is called ?pausing dclk .? the enhanced configuration device fl ash memories feature a 90-ns access time (approximately 10 mhz). hence, the flash read bandwidth is limited to about 160 megabits per second (mbps) (16-bit flash data bus, dq[] , at 10 mhz). however, the configuration speeds supported by altera fpgas are much higher and translate to hi gh configuration write bandwidths. for instance, 100-mhz stratix fpp configuration requires data at the rate of 800 mbps (8-bit data[] bus at 100 mhz). this is much higher than the 160 mbps the flash memory can support , and is the limiting factor for configuration time. compression increases the effective flash read bandwidth since the same amount of configuration data takes up less space in the flash memory after compression. since stratix configuration data compression ratios are approximately two, the effective read bandwidth doubles to about 320 mbps. finally, the configurat ion controller also ma nages errors during configuration. a conf_done error occurs when the fpga does not de- assert its conf_done signal within 64 dclk cycl es after the last bit of configuration data is transmitted. when a conf_done error is detected, the controller pulses the oe line low, which pulls nstatus low and triggers another configuration cycle. a cyclic redundancy check (crc) er ror occurs when the fpga detects corruption in the configuration data. th is corruption could be a result of noise coupling on the board such as poor signal integrity on the configuration signals. when this er ror is signaled by the fpga (by driving the nstatus line low), the controller stops configuration. if the auto-restart configuration after error option is enabled in the fpga, it releases its nstatus signal after a reset time-out period and the controller attempts to reconfigure the fpga. after the fpga configuration process is complete, the controller drives dclk low and the data[] pins high. additionally, the controller tri- states its internal interface to the fl ash memory, enables the weak internal pull-ups on the flash address and control lines, and enables bus-keep circuits on flash data lines. the following sections briefly desc ribe the different configuration schemes supported by th e enhanced configuratio n device: fpp, ps, and concurrent configuration.
2?6 altera corporation configuration handbook, volume 2 august 2005 functional description f for detailed information on usin g these schemes to configure your altera fpga, refer to the appropri ate fpga family chapter in the configuration handbook . configuration signals table 2?3 lists the configuration signal connections between the enhanced configuration device and altera fpgas. table 2?3. configuration signals enhanced configuration device pin altera fpga pin description data[] data[] configuration data transmitted from the configuration device to t he fpga, which is latched on the rising edge of dclk . dclk dclk configuration device generated clock used by the fpga to latch configuration data provided on the data[] pins. ninit_conf nconfig open-drain output from the configuration device that is used to initiate fpga reconfiguration using the initiate configuration ( init_conf ) jtag instruction. this connection is not needed if the init_conf jtag instruction is not needed. if n init_conf is not connected to nconfig , nconfig must be tied to v cc either directly or through a pull-up resistor. oe nstatus open-drain bidirectional configuration status signal, which is driven low by either device during por and to signal an error during configuration. low pulse on oe resets the enhanced configuration device controller. ncs conf_done configuration done output signal driven by the fpga.
altera corporation 2?7 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet fast passive parallel configuration stratix series and apex ii devices ca n be configured us ing the enhanced configuration device in fpp mode . in this mode, the enhanced configuration device sends a byte of data on the data[7..0] pins, which connect to the data[7..0] input pins of the fpga, per dclk cycle. stratix series and apex ii fpgas receive byte-wide configuration data per dclk cycle. figure 2?2 shows the enhanced configuration device in fpp configuration mode. in this figure, the external flash interface is not used and hence most flash pins are left unconnected (with the few noted exceptions). for specific de tails on configuration interface connections including pull-up resistor values, supply voltages, and msel pin settings, refer to the appropri ate fpga family chapter in the configuration handbook.
2?8 altera corporation configuration handbook, volume 2 august 2005 functional description figure 2?2. fpp configuration notes to figure 2?2 : (1) the v cc should be connected to the same suppl y voltage as the co nfiguration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active. this means an external p ull-up resistor is not required on the ninit_conf / nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ? ii software. to turn off the inte rnal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) for porsel , pgm[] , and exclk pin connections, refer to table 2?9 . (5) in the 100-pin pqfp package, you must externally connect the following pins: c-a0 to f-a0 , c-a1 to f-a1 , c-a15 to f-a15 , c-a16 to f-a16 , and byte# to v cc . additionally, you must make the following pin connections in both 100-pin pqfp and 88-pin ultra fineline bga packages: c-rp# to f-rp# , c-we# to f-we# , tm1 to v cc , tm0 to gnd, and wp# to v cc . (6) connect the fpga msel[] input pins to select the fpp configuratio n mode. for details, refer to the appropriate fpga family chapter in the configuration handbook. multiple fpgas can be configured us ing a single enhanced configuration device in fpp mode. in this mode, multiple stratix series and/or apex ii fpgas are cascaded togeth er in a daisy chain. enhanced configuration device dclk data[7..0] oe ncs ninit_conf (2) msel dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd gnd (3) (3) nce exclk stratix series or apex ii device we#c rp#c wp# porsel pgm[2..0] tmo we#f rp#f a[20..0] ry/by# ce# oe# dq[15..0] v cc n.c. n.c. n.c. n.c. n.c. byte# (5) tm1 (3) (3) c-a0 (5) c-a1 (5) c-a15 (5) c-a16 (5) a0-f a1-f a15-f a16-f (1) (1) n (6) (1) nceo n.c. (4) (4) (4) vccw v cc (1)
altera corporation 2?9 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet after the first fpga comp letes configuration, its nceo pin asserts to activate the second fpga?s nce pin, which prompts the second device to start capturing configuration da ta. in this setup, the fpgas conf_done pins are tied together, and hence all devices initialize and enter user mode simultaneously. if the enhanced configuration device or one of the fpgas detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nstatus pins are tied together. 1 while altera fpgas can be cascad ed in a configuration chain, the enhanced configuration de vices cannot be cascaded to configure larger devices/chains. f for configuration schematics and more information on multi-device fpp configuration, refer to the appropri ate fpga family chapter in the configuration handbook . passive serial configuration stratix series, cyclone series, apex ii, apex 20kc, apex 20ke, apex 20k, and flex 10k devices can be configured using enhanced configuration devices in the ps mode. this mode is similar to the fpp mode, with the exception that only one bit of data ( data[0] ) is transmitted to the fpga per dclk cycle. the remaining data[7..1] output pins are unused in this mode and drive low. the configuration schematic for ps co nfiguration of a single fpga or single serial chain is identical to the fpp schematic (with the exception that only data[0] output from the enhanced configuration device connects to the fpga data0 input pin; remaining data[7..1] pins are left floating). f for configuration schematics and more information on multi-device ps configuration, refer to the appropri ate fpga family chapter in the configuration handbook . concurrent configuration the enhanced configuratio n device supports concurrent configuration of multiple fpgas (or fpga chains) in ps mode. concurrent configuration is when the enhanced configuration de vice simultaneously outputs n bits of configuration data on the data[n-1..0] pins (n = 1, 2, 4, or 8), and each data[] line serially configures a different fpga (chain). the number of concurrent serial chains is user-defined via the quartus ii software and can be any number between 1 and 8. for example, three concurrent chains you can select the 4-bit ps mode, and connect the least
2?10 altera corporation configuration handbook, volume 2 august 2005 functional description significant data bits to the fpgas or fpga chains. leave the most significant data bit ( data[3] ) unconnected. similarly, for 5-, 6- or 7-bit concurrent chains you can select the 8-bit ps mode. figure 2?3 shows the schematic for configuring multiple fpgas concurrently in the ps mode using an enhanced configuration device. f for specific details on configuration interface connections including pull-up resistor values , supply voltages, and msel pin settings, refer to the appropriate fpga family chapter in the configuration handbook .
altera corporation 2?11 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet figure 2?3. concurrent configuration of multiple fpgas in ps mode (n = 8) notes to figure 2?3 : (1) connect v cc to the same supply voltage as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active. this means an external p ull-up resistor is not required on the ninit_conf / nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) for porsel , pgm[] , and exclk pin connections, refer to table 2?9 . (5) in the 100-pin pqfp package, you must externally connect the following pins: c-a0 to f-a0 , c-a1 to f-a1 , c-a15 to f-a15 , c-a16 to f-a16 , and byte# to v cc . additionally, you must make the following pin connections in both 100-pin pqfp and 88-pin ultra fineline bga packages: c-rp# to f-rp# , c-we# to f-we# , tm1 to v cc , tm0 to gnd, and wp# to v cc . (6) connect the fpga msel[] input pins to select the ps configuration mode. for details, refer to the appropriate fpga family chapter in the configuration handbook. dclk data 0 nstatus conf_done nconfig v cc gnd (3) nce (3) fpga0 v cc dclk data0 nconfig nce dclk data0 gnd gnd fpga1 fpga7 enhanced configuration device dclk data0 oe ncs ninit_conf (2) we#c rp#c we#f rp#f a[20..0] ry/by# ce# oe# dq[15..0] data1 nstatus conf_done nstatus conf_done nconfig nce data 7 n.c . n.c . n.c. n.c . n.c. (3) (3) exclk porsel pgm[2..0] gnd tmo wp# v cc vccw byte# (5) tm1 c-a0 (5) c-a1 (5) c-a15 (5) c-a16 (5) a0-f a1-f a15-f a16-f msel msel msel n n n (6) (6) (6) (1) (1) nceo n.c. nceo n.c. nceo n.c. (1) (4) (4) (4) v cc (1)
2?12 altera corporation configuration handbook, volume 2 august 2005 functional description table 2?4 summarizes the concurrent ps configuration modes supported in the enhanced configuration device. f for configuration schematics and more information on concurrent configuration, refer to using altera enhanced configuration devices , chapter 3 in volume 2 of the configuration handbook . or the appropriate fpga family chapter in the configuration handbook . external flash interface the enhanced configuration devices support external fpga or processor access to its flash memory. the unused portions of the flash memory can be used by the external device to stor e code or data. this interface can also be used in systems that implement remote configuration capabilities. configuration data within a particular configuration page can be updated via the external flash in terface and the system could be reconfigured with the new fpga image. this interface is also useful to store nios boot code and/or application code. f for more information on the stratix remote configuration feature, refer to the using remote system configuration with stratix & stratix gx devices chapter of the stratix device handbook . the address, data, and control ports of the flash memory are internally connected to the enhanced configuratio n device controller and to external device pins. an external source can drive these external device pins to access the flash memory when th e flash interface is available. this external flash in terface is a shared bus interface with the configuration controller chip. the conf iguration controller is the primary bus master. since there is no bus arbi tration support, the external device can only access the flash interface when the controller has tri-stated its table 2?4. enhanced configuration devices in ps mode mode name mode (n =) (1) used outputs unused outputs passive serial mode 1 data0 data[7..1] drive low multi-device passive serial mode 2 data[1..0] data[7..2] drive low multi-device passive serial mode 4 data[3..0] data[7..4] drive low multi-device passive serial mode 8 data[7..0] - note to ta b l e 2 ? 4 : (1) this is the number of valid data outputs for each configuration mode.
altera corporation 2?13 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet internal interface to the flash. simu ltaneous access by the controller and the external device will cause conten tion, and result in configuration and programming failures. since the internal flash interface is di rectly connected to the external flash interface pins, controller flash access cycles will toggle the external flash interface pins. the external device must be able to tri-state its flash interface during these times and ignore transitions on the flash interface pins. 1 the external flash interface si gnals cannot be shared between multiple enhanced configuration devices because this causes contention during in-system pr ogramming and configuration. during these times, the controll er chips inside the enhanced configuration devices are acti vely accessing flash memory. therefore, enhanced configur ation devices do not support shared flash bus interfaces. the enhanced configuration device cont roller chip accesses flash memory during: fpga configuration?reading configuration data from flash jtag-based flash programming?storin g configuration data in flash at por?reading option bits from flash during these times, the external fpga/processor must tri-state its interface to the flash memory. after configuration and programming, the enhanced configuration device?s controll er tri-states the internal interface and goes into an idle mode. to interrupt a configuration cycle in order to access the flash via the external flas h interface, the external device can hold the fpga?s nconfig input low. this keeps the configuration device in reset by holding the nstatus - oe line low, allowing external flash access. f for further details on the software support for the external flash interface feature, refer to using altera enhanced configuration devices , chapter 3 in volume 2 of the configuration handbook . for details on flash commands, timing, memory organization, and writ e protection features, refer to the appropriate flash data sheet (sharp lhf16306 for epc16 devices and micron mt28f400b3 for ep c4 devices) on the altera web site at www.altera.com . figure 2?4 shows a fpp configuration schematic with the external flash interface being used.
2?14 altera corporation configuration handbook, volume 2 august 2005 functional description figure 2?4. fpp configuration with external flash interface note (1) notes to figure 2?4 : (1) for external flash interface support in epc8 enhanc ed configuration device, contact altera applications. (2) pin a20 in epc16 devices, pins a20 and a19 in epc8 devices, and pins a20 , a19 , and a18 in epc4 devices should be left floating. these pins should not be connect ed to any signal, i.e., they are no-connect pins. (3) in the 100-pin pqfp package, you must externally connect the following pins: c-a0 to f-a0 , c-a1 to f-a1 , c-a15 to f-a15 , c-a16 to f-a16 , and byte # to v cc . additionally, you must make the following pin connections in both 100-pin pqfp and 88-pin ultra fineline bga packages: c-rp# to f-rp# , c-we# to f-we# , tm1 to v cc , tm0 to gnd, and wp# to v cc . (4) for porsel , pgm[] , and exclk pin connections, refer to table 2?9 . dynamic configuration (page mode) the dynamic configuration or page mode feature allows the enhanced configuration device to store up to eight different sets of designs for all the fpgas in your system. you can then choose which page (set of configuration files) the enhanced configuration device should use for fpga configuration. msel dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd nce stratix series or apex ii device we# rp# a[20..0] ry/by# ce# oe# dq[15..0] pld or processor enhanced configuration device dclk data[7..0] oe ncs ninit_conf we#c rp#c we#f rp#f a[20..0] (2) ry/by# ce# oe# dq[15..0] gnd exclk wp# porsel pgm[2..0] tmo v cc vccw byte# (3) tm1 c-a0 (3) c-a1 (3) c-a15 (3) c-a16 (3) a0-f a1-f a15-f a16-f n nceo n.c. (4) (4) (4) v cc
altera corporation 2?15 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet dynamic configuration or the page mode feature enables you to store a minimum of two pages: a factory defa ult or fail-safe configuration, and an application configuration. the fa il-safe configuration page could be programmed during system prod uction, while the application configuration page could support remote or local updates. these remote updates could add or enhance syst em features and performance. however, with remote update capabi lities comes the risk of possible corruption of configuration data. in the event of such a corruption, the system could automatically switch to the fail-safe configuration and avoid system downtime. the enhanced configuration device page mode feature works with the stratix remote system configuration fe ature, to enable intelligent remote updates to your systems. f for more information on remotely updating stratix fpgas, refer to using remote system configuration with stratix & stratix gx devices in the stratix device handbook . the three pgm[2..0] input pins control which page is used for configuration, and these pins are sampled at the start of each configuration cycle when oe goes high. the page mode selection allows you to dynamically reconfigure the functionality of your fpga(s) by switching the pgm[2..0] pins and asserting nconfig . page 0 is defined as the default page and the pgm[2] pin is the most significant bit (msb). 1 the pgm[2..0] input pins must not be left floating on your board, regardless of whether this feature is used or not. when this feature is not used, connect the pgm[2..0] pins to gnd to select the default page 000. the enhanced configuration device pages are dynamically sized regions in memory. the start address and length of each page is programmed into the option bit space of the flash me mory during initial programming. all subsequent configuration cycles will sample the pgm[] pins and use the option bit information to jump to the start of the corresponding configuration page. each page must have configuration files for all fpgas in your system that are connected to that enhanced configuration device. for example, if your system requ ires three configuration pages and includes two fpgas, each page will store two sram object files ( .sof ) for a total of six sofs in the configuration device.
2?16 altera corporation configuration handbook, volume 2 august 2005 functional description furthermore, all enhanced configur ation device conf iguration schemes (ps, fpp, and concurrent ps) are supported with the page mode feature. the number of pages and/or devices that can be configured using a single enhanced configuration device is only limited by the size of the flash memory. f for detailed information on the page mode feature implementation and programming file generation steps using quartus ii software, refer to using altera enhanced configuration devices , chapter 3 in volume 2 of the configuration handbook . real-time decompression enhanced configuration devices support on-chip real time decompression of configuration data. fpga configuration data is compressed by the quartus ii soft ware and stored in the enhanced configuration device. during configuration, the decompression engine inside the enhanced configuration device will decompress or expand configuration data. this feature increases the effective configuration density of the enhanced configuration device up to 7, 15, or 30 mbits in the epc4, epc8, and epc16, respectively. the enhanced configuration device also supports a parallel 8-bit data bus to the fpga to reduce configuration time. however, in some cases, the fpga data transfer time is limite d by the flash read bandwidth. for example, when configuring an apex ii device in fpp (byte-wide data per cycle) mode at a configuration speed of 66 mhz, the fpga write bandwidth is equal to 8 bits 66 mhz = 528 mbps. the flash read interface, however, is limited to approximately 10 mhz (since the flash access time is ~90 ns). this tran slates to a flash read bandwidth of 16 bits 10 mhz = 160 mbps. hence, th e configuration time is limited by the flash read time. when configuration data is compressed , the amount of data that needs to be read out of the flash is reduced by about 50 % . if 16 bits of compressed data yields 30 bits of uncompress ed data, the flash read bandwidth increases to 30 bits 10 mhz = 300 mbps, reducing overall configuration time. you can enable the controller's deco mpression feature in the quartus ii software, configuration device options window by turning on compression mode .
altera corporation 2?17 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet 1 the decompression feature supported in the enhanced configuration devices is different from the decompression feature supported by the stra tix ii fpgas an d the cyclone series. when configuring stratix ii fpgas or the cyclone series using enhanced configuration devices, altera recommends enabling decompression in stratix ii fpgas or the cyclone series only for faster configuration. the compression algorithm used in al tera devices is optimized for fpga configuration bitstreams. since fpgas have several layers of routing structures (for high performance and easy routability), large amounts of resources go unused. these unused routing and logic resources as well as un-initialized memory structures result in a large number of configuration ram bits in the disabled state. altera's proprietary compression algorithm takes advantag e of such bitstream qualities. the general guideline for effectiveness of compression is the higher the device logic/routing utilization, th e lower the compression ratio (where compression ratio is defined as original bitstream size divided by the compressed bit-stream size). for stratix designs, based on a suite of designs with varying amounts of logic utilization, the minimum compression ratio was observed to be 1.9 or a ~47 % size reduction for these designs. table 2?5 shows sample compression ratios from a suite of stratix designs. these numbers serve as a guideline (not a specification) to help you allocate sufficient configuration memory to stor e compressed bitstreams. table 2?5. stratix compression ratios note (1) minimum average logic utilization 98 % 64 % compression ratio 1.9 2.3 % size reduction 47 % 57 % note to ta b l e 2 ? 5 : (1) these numbers are preliminary. they are intended to serve as a guideline, not a specification.
2?18 altera corporation configuration handbook, volume 2 august 2005 functional description programmable configuration clock the configuration clock ( dclk ) speed is user programmable. one of two clock sources can be used to synthesize the configuration clock; a programmable oscillator or an external clock input pin ( exclk ). the configuration clock frequency can be further synthesize d using the clock divider circuitry. this clock can be divided by the n counter to generate your dclk output. the n divider supports all integer dividers between 1 and 16, as well as a 1.5 divider and a 2.5 divider. the duty cycle for all clock division s other than non-integer divisions is 50 % (for the non- integer dividers, the duty cycle will not be 50%). see figure 2?5 for a block diagram of the clock divider unit. figure 2?5. clock divider unit the dclk frequency is limited by the maximum dclk frequency the fpga supports. f the maximum dclk input frequency supported by the fpga is specified in the appropriate fpga family chapter in the configuration handbook . configuration device clock divider unit divide by n external clock (up to 133 mhz) internal oscillator 10 mhz 33 mhz 50 mhz 66 mhz dclk
altera corporation 2?19 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet the controller chip features a prog rammable oscillator that can output four different frequencies. the variou s settings generate clock outputs at frequencies as high as 10, 33, 50, and 66 mhz, as shown in table 2?6 . clock source, oscillator frequency, an d clock divider (n) settings can be made in the quartus ii software, by accessing the configuration device options inside the device settings window or the convert programming files window. the same window can be used to select between the internal oscilla tor and the external clock ( exclk ) input pin as your configuration clock source. the default setting selects the internal oscillator at the 10 mhz se tting as the clock source, with a divide factor of 1. f for more information on making the configuration clock source, frequency, and divider settings, refer to using altera enhanced configuration devices , chapter 3 in volume 2 of the configuration handbook . flash in-system programming (isp) the flash memory inside enhanced configuration devices can be programmed in-system via the jtag interface and the external flash interface. jtag-based programming is facilitated by the configuration controller in the enhanced configurat ion device. external flash interface programming requires an external proc essor or fpga to control the flash. 1 the enhanced configuration de vice flash memory supports 100,000 erase cycles. jtag-based programming the ieee std. 1149.1 jtag boundary scan is im plemented in enhanced configuration devices to facilitate th e testing of its interconnection and functionality. enhanced configuratio n devices also support the isp mode. the enhanced configuration device is compliant with th e ieee std. 1532 draft 2.0 specification. table 2?6. internal oscillator frequencies frequency setting min (mhz) typ (mhz) max (mhz) 10 6.4 8.0 10.0 33 21.0 26.5 33.0 50 32.0 40.0 50.0 66 42.0 53.0 66.0
2?20 altera corporation configuration handbook, volume 2 august 2005 functional description the jtag unit of the configuration controller communicates directly with the flash memory. the controller processes the isp instructions and performs the necessary flash operat ions. the enhanced configuration devices support a maximum jtag tck frequency of 10 mhz. during jtag-based isp, the external flash interface is not available. before the jtag interface programs the flash memory, an optional jtag instruction (pendcfg) can be used to assert the fpga?s nconfig pin (via the ninit_conf pin). this will keep the fpga in reset and terminate any internal flash access. th is function prevents contention on the flash pins when both jtag isp and an external fpga/processor try to access the flash simultaneously. the ninit_conf pin is released when the initiate configuration ( ninit_conf ) jtag instruction is updated. as a result, the fpga is configured with the new configuration data stored in flash. this function can be ad ded to your programming fi le in the quartus ii software by enabling the initiate configuration after programming option in the programmer options window (options menu). programming via external flash interface this method allows parallel programm ing of the flash memory (using the 16-bit data bus). an external proc essor or fpga acts as the flash controller and has access to programming data (via a communication link such as uart, ethernet, and pci). in addition to the program, erase, and verify operations, the external fl ash interface supports block/sector protection instructions. f for information on protection comman ds, areas, and lock bits, refer to the appropriate flash memory data sheet (sharp lhf16506 for epc16 devices and micron mt28f400b3 for ep c4 devices) on the altera web site at www.altera.com . external flash interface programmi ng is only allowed when the configuration controller has relinquished flash access (by tri-stating its internal interface). if the controlle r has not relinquished flash access (during configuration or jtag-based isp), you must hold the controller in reset before initiating external programming. the controller can be reset by holding the fpga nconfig line at a logic low level. this keeps the controller in reset by holding the nstatus - oe line low, allowing external flash access. 1 if initial programming of the enhanced configuration device is done in-system via the external flash interface, the controller must be kept in reset by driving the fpga nconfig line low to prevent contention on the flash interface.
altera corporation 2?21 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet pin description tables 2?7 through 2?9 describe the enhanced co nfiguration device pins. these tables include configuration inte rface pins, external flash interface pins, jtag interface pins, and other pins. table 2?7. configuration interface pins pin name pin type description data[7..0] output this is the configuration data output bus. data changes on each falling edge of dclk . data is latched into the fpga on the rising edge of dclk . dclk output the dclk output pin from the enhanced configuration device serves as the fpga configuration clock. data is latched by the fpga on the rising edge of dclk . ncs input the ncs pin is an input to the enhanced configuration device and is connected to the fpga?s conf_done signal for error detection after all configuration data is transmitted to t he fpga. the fpga will always drive ncs and oe low when nconfig is asserted. this pin contains a programmable internal weak pull-up resistor that can be disabled/enabled in the quartus ii software through the disable ncs and oe pull-ups on configuration device option. ninit_conf open-drain output the ninit_conf pin can be connected to the nconfig pin on the fpga to initiate configuration from the enhanced configuration device via a private jtag instruction. this pin contains an internal weak pull-up resistor that is always active. the init_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a pull-up resistor. oe open-drain bidirectional this pin is driven low when por is no t complete. a user-selectable 2-ms or 100-ms counter holds off the release of oe during initial power up to permit voltage levels to stabilize. por time can be extended by externally holding oe low. oe is connected to the fpga nstatus signal. after the enhanced configuration device controller releases oe , it waits for the nstatus - oe line to go high before starting the fpga configuration process. this pin contains a progra mmable internal weak pull-up resistor that can be disabled/enabled in the quartus ii software through the disable ncs and oe pull-ups on configuration device option.
2?22 altera corporation configuration handbook, volume 2 august 2005 pin description table 2?8. external flash interface pins (part 1 of 2) pin name pin type description a[20..0] input these pins are the address input to the flash memory for read and write operations. the addresses are internally latched during a write cycle. when the external flash interface is not used, leave these pins floating (with the few exceptions noted below ). these flash address, data, and control pins are internally connecte d to the configuration controller. in the 100-pin pqfp package, four address pins ( a0 , a1 , a15 , a16 ) are not internally connected to the c ontroller. these loop back connections must be made on the board between the c-a[] and f-a[] pins even when not using the external flash in terface. all other address pins are connected internal to the package. all address pins are connected internal ly in the 88-pin ultra fineline bga package. pin a20 in epc16 devices, pins a20 and a19 in epc8 devices, and pins a20 , a19 , and a18 in epc4 devices are no-connects. these pins should be left floating on the board. dq[15..0] bidirectional this is the flash data bus interface between the flash memory and the controller. the controller or an external source drives dq[15..0] during the flash command and the data write bus cycles. during the data read cycle, the flash memory drives the dq[15..0] to the controller or external device. leave these pins floating on the board when the external flash interface is not used. ce# input active low flash input pin that ac tivates the flash memory when asserted. when it is high, it deselects the de vice and reduces power consumption to standby levels. this flash input pi n is internally connected to the controller. leave this pin floating on the board when the external flash interface is not used. rp# (1) input active low flash input pin that resets the flash when asserted. when high, it enables normal operation. when low, it inhibits write operation to the flash memory, which provides data protection during power transitions. this flash input is not internally connected to the controller. hence, an external loop back connection between c-rp# and f-rp# must be made on the board even when you are not using the external flash interface. when using the external flash interface, connect the external device to the rp# pin with the loop back.
altera corporation 2?23 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet oe# input active low flash control input that is asserted by the controller or external device during flash read cycles. when a sserted, it enables the drivers of the flash output pins. leave this pin floating on the board when the external flash interface is not used. we# (1) input active low flash write strobe asserted by the controller or external device during flash write cycles. when asserted, it controls writes to the flash memory. in the flash memory, addresses and data are latched on the rising edge of the we# pulse. this flash input is not internally connected to the controller. hence, an external loop back connection between c-we# and f-we# must be made on the board even when you are not using the external flash interface. when using the external flash interface, connect the external device to the we# pin with the loop back. wp# input this pin is usually tied to v cc or ground on the board. the controller does not drive this pin because it could cause contention. connection to v cc is recommended for faster block erase/programming times and to allow programming of the flash bottom boot block, which is required when programming the device using the quartus ii software. this pin should be connected to v cc even when the external flash interface is not used. vccw supply block erase, full chip erase, word write, or lock bit configuration power supply. connect this pin to the 3.3-v v cc supply, even when you are not using the external flash interface. ry/by# output flash asserts this pin when a writ e or erase operation is complete. this pin is not connected to the controller. leave this pin floating when the ex ternal flash interface is not used. byte# input this is flash byte enable pi n and is only available for enhanced configuration devices in the 100-pin pqfp package. this pin must be connected to v cc on the board even when you are not using the external flash interface (the controller uses the flash in 16-bit mode). note to ta b l e 2 ? 8 : (1) these pins can be driven to 12 v during production testin g of the flash memory. since the controller cannot tolerate the 12-v level, connections from the co ntroller to these pins are not made internal to the package. instead they are available as two separate pins. you must connect the two pins at the board level (for example, on the printed circuit board (pcb), connect the c-we# pin from controller to f-we# pin from the flash memory). table 2?8. external flash interface pins (part 2 of 2) pin name pin type description
2?24 altera corporation configuration handbook, volume 2 august 2005 power-on reset (por) power-on reset (por) the por circuit keeps the system in reset until power supply voltage levels have stabilized. the por time consists of the v cc ramp time and a user programmable por delay counter. when the supply is stable and the por counter expires, the por circuit releases the oe pin. the por time can be further extended by an external device by driving the oe pin low. 1 do not execute jtag or isp instructions until por is complete. table 2?9. jtag interface pins and other required c ontroller pins pin name pin type description tdi input this is the jtag data input pin. connect this pin to v cc if the jtag circuitry is not used. tdo output this is the jtag data output pin. do not connect this pin if the jtag ci rcuitry is not used (leave floating). tck input this is the jtag clock pin. connect this pin to gnd if the jtag circuitry is not used. tms input this is the jtag mode select pin. connect this pin to v cc if the jtag circuitry is not used. pgm[2..0] input these three input pins select one of the eight pages of configuration data to configure the fpga(s) in the system. connect these pins on the board to select the page specified in the quartus ii software when generating the enhanced configuration device pof. pgm[2] is the msb. default selection is page 0; pgm[2..0]=000 . these pins must not be left floating. exclk input optional external clock input pin that can be used to generate the configuration clock ( dclk ). when an external clock source is not us ed, connect this pin to a valid logic level (high or low) to prevent a floating input buffer. porsel input this pin selects a 2-ms or 100-ms por counter delay during power up. when porsel is low, por time is 100-ms. when porsel is high, por time is 2 ms. this pin must be connected to a valid logic level. tm0 input for normal operation, this test pin must be connected to gnd. tm1 input for normal operating, this test pin must be connected to v cc .
altera corporation 2?25 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet the enhanced configuration device supports a programmable por delay setting. you can set the por delay to th e default 100-ms setting or reduce the por delay to 2 ms for systems that require fast power-up. the porsel input pin controls this por delay; a logic high level selects the 2-ms delay, while a logic low level selects the 100-ms delay. the enhanced configuration device can enter reset under the following conditions: the por reset starts at initial power-up during v cc ramp-up or if v cc drops below the minimum operating condition anytime after v cc has stabilized the fpga initiates reconfiguration by driving nstatus low, which occurs if the fpga detects a crc error or if the fpga?s nconfig input pin is asserted the controller detects a configuration error and asserts oe to initiate re-configuration of the altera fpga (for example when conf_done stays low after all configuration data has been transmitted) power sequencing altera requires that you power-up the fpga's v ccint supply before the enhanced configuration device's por expires. power up needs to be controlled so that the enhanced configuration device?s oe signal goes high after the conf_done signal is pulled low. if the eepc device exits por before the fpga is powered up, the conf_done signal will be high since the pull-up resistor is holding this signal high. when the enhanced configuration device exits por, oe is released and pulled high by a pu ll-up resistor. since the enhanced configuration device samples the ncs signal on the rising edge of oe , it detects a high level on conf_done and enters an idle mode. data and dclk outputs will not toggle in this state and configuration will not begin. the enhanced configuration device will only exit this mode if it is powered down and then powered up correctly. 1 to ensure the enhanced co nfiguration device enters configuration mode properly, you need to ensure that the fpga completes power-up before the enhanced configuration device exits por. the pin-selectable por time feature is useful for ensuring this power-up sequence. the enhanced configuration device has two por settings, 2 ms when porsel is set to a high level and 100 ms when porsel is set to a low level. for more margin, the 100-ms setting can be selected to allow the fpga to power-up before configuration is attempted.
2?26 altera corporation configuration handbook, volume 2 august 2005 programming & configuration file support alternatively, a power monitoring circ uit or a power good signal can be used to keep the fpga?s nconfig pin asserted low until both supplies have stabilized. this ensures the correct power up sequence for successful configuration. programming & configuration file support the quartus ii development software provides programming support for the enhanced configuration device and automatically generates the pof files for the epc4, epc8, and epc16 devices. in a multi-device project, the software can combine the sof files for multiple stratix series, cyclone series, apex ii, apex 20k, mercury, acex 1k, and flex 10k fpgas into one programming file for th e enhanced configuration device. f refer to using altera enhanced co nfiguration devices , chapter 3 in volume 2 of the configuration handbook or the software settings section in the configuration handbook for details on generating programming files. enhanced configuration devices can be programmed in-system through its industry-standard 4-pin jtag in terface. the isp feature in the enhanced configuration device provides ease in prototyping and updating fpga functionality. after programming an enhanced configuration device in-system, fpga configuration can be initiated by in cluding the enhanced configuration device?s jtag init_conf instruction ( table 2?10 ). the isp circuitry in the enhanced configuration device is compliant with the ieee std. 1532 specification. the ieee std. 1532 is a standard that allows concurrent isp between devices from multiple vendors. table 2?10. enhanced configuration device jtag instructions (part 1 of 2) note (1) jtag instruction opcode description sample/preload 00 0101 0101 allows a snapshot of the state of the enhanced configuration device pins to be captured and examined during normal device operation and permits an initial data pattern output at the device pins. extest 00 0000 0000 allows the exter nal circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing results at the input pins. bypass 11 1111 1111 places the 1-bi t bypass register between the tdi and the tdo pins, which allow the bst data to pass synchronously through a selected device to adjacent devices during normal device operation.
altera corporation 2?27 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet f for more information on the enha nced configuration device jtag support, refer to the bsdl files provided at the altera web site. enhanced configuration de vices can also be programmed by third-party flash programmers or on-board proc essors using the external flash interface. programming files (pof) can be converted to an intel hex format file ( .hexout ) using the quartus ii convert programming files utility, for use with the programmers or processors. idcode 00 0101 1001 selects the device idcode register and places it between tdi and tdo , allowing the device idcode to be serially shifted out to tdo . the device idcode for all enhanced configuration devices is the same and shown below: 0100a0ddh usercode 00 0111 1001 selects the userco de register and places it between tdi and tdo , allowing the usercode to be serially shifted out the tdo . the 32-bit usercode is a programmable user-defined pattern. init_conf 00 0110 0001 this function initiates the fpga re-configuration process by pulsing the ninit_conf pin low, which is connected to the fpga(s) nconfig pin(s). after this instruction is updated, the ninit_conf pin is pulsed low when the jtag state machine enters run-test/idle state. the ninit_conf pin is then released and nconfig is pulled high by the resistor after the jtag state machine goes out of run-test/idle state. the fpga configuration starts after nconfig goes high. as a result, the fpga is configured with the new configuration data stored in flash via isp. this function can be added to your programming file (pof, jam, jbc) in the quartus ii software by enabling the initiate configuration after programming option in the programmer options window (options menu). pendcfg 00 0110 0101 this optional function can be used to hold the ninit_conf pin low during jtag-based isp of the enhanced configuration device. this feature is useful when the external flash interface is controlled by an external fpga/processor. this function prevents contention on the flash pins when both the controller and external device try to access the flash simultaneously. before the enhanced configuration devi ce?s controller can access the flash memory, the external fpga/proce ssor needs to tri-state its interface to flash.this can be ensured by resetting the fpga using the ninit_conf , which drives the nconfig pin and keeps the external fpga/processor in the ?reset? state. the ninit_conf pin is released when the initiate configuration ( init_conf ) jtag instruction is issued. note to table 2?10 : (1) enhanced configuration device instruction register length is 10 and boun dary scan length is 174. table 2?10. enhanced configuration device jtag instructions (part 2 of 2) note (1) jtag instruction opcode description
2?28 altera corporation configuration handbook, volume 2 august 2005 ieee std. 1149.1 (jtag) boundary-scan you can also program the enhanced configuration devices using the quartus ii software, the altera programming unit (apu), and the appropriate configuration de vice programming adapter. table 2?11 shows which programming adapte r to use with each enhanced configuration device. ieee std. 1149.1 (jtag) boundary-scan the enhanced configuration device provides jtag bst circuitry that complies with the ieee std. 1149.1 -1990 specification. jtag boundary- scan testing can be performed before or after configuration, but not during configuration. figure 2?6 shows the timing requirements for the jtag signals. figure 2?6. jtag timing waveforms table 2?11. table 10. programming adapters device package adapter epc16 88-pin ultra fineline bga plmuepc-88 100-pin pqfp plmqepc-100 epc8 100-pin pqfp plmqepc-100 epc4 100-pin pqfp plmqepc-100 tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
altera corporation 2?29 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet table 2?12 shows the timing parameters and values for the enhanced configuration device. table 2?12. jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high-impedance to valid output 25 ns t jsxz update register valid out put to high impedance 25 ns
2?30 altera corporation configuration handbook, volume 2 august 2005 timing information timing information figure 2?7 shows the configuration timi ng waveform when using an enhanced config uration device. figure 2?7. configuration timing waveform using an enhanced configuration device notes to figure 2?7 : (1) the enhanced configura tion device will drive dclk low after configuration. (2) the enhanced configuration device will data[] high after configuration. table 2?13 defines the timing parameters when using the enhanced configuration devices. f for flash memory (external flash inte rface) timing information, please refer to the corresponding flash data sh eet on the altera web site (sharp lhf16j06 for epc16 devices and micr on mt28f400b3 for epc4 devices). tri-state user mode t loe t lc t hc t ce t oe bit/byte bit/byte 2 n bit/byte 1 driven hi g h tri-state oe/nstatus ncs/conf_done dclk data user i/o init_done ninit_conf or vcc/nconfig (1) (2) table 2?13. enhanced configuration device c onfiguration parameters (part 1 of 2) symbol parameter condition min typ max unit f dclk dclk frequency 40 % duty cycle 66.7 mhz t dclk dclk period 15 ns t hc dclk duty cycle high time 40 % duty cycle 6 ns t lc dclk duty cycle low time 40 % duty cycle 6 ns t ce oe to first dclk delay 40 ns t oe oe to first data available 40 ns t oh dclk rising edge to data change (1) ns t cf (2) oe assert to dclk disable delay 277 ns t df (2) oe assert to data disable delay 277 ns
altera corporation 2?31 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet operating conditions tables 2?14 through 2?18 provide information on absolute maximum ratings, recommended operating cond itions, dc operating conditions, supply current values, and pin capa citance data fo r the enhanced configuration devices. t re (3) dclk rising edge to oe 60 ns t loe oe assert time to assure reset 60 ns f eclk exclk input frequency 40 % duty cycle 133 mhz t eclk exclk input period 7.5 ns t eclkh exclk input duty cycle high time 40 % duty cycle 3.375 ns t eclkl exclk input duty cycle low time 40 % duty cycle 3.375 ns t eclkr exclk input rise time 133 mhz 3 ns t eclkf exclk input fall time 133 mhz 3 ns t por (4) por time 2 ms 1 2 3 ms 100 ms 70 100 120 ms notes to table 2?13 : (1) to calculate t oh , use the following equation: t oh = 0.5 ( dclk period) - 2.5 ns. (2) this parameter is used for crc error detection by the fpga. (3) this parameter is used for conf_done error detection by the enhanced configuration device. (4) the fpga v ccint ramp time should be less than 1-ms for 2-ms po r, and it should be less than 70 ms for 100-ms por. table 2?13. enhanced configuration device c onfiguration parameters (part 2 of 2) symbol parameter condition min typ max unit table 2?14. enhanced configuration devi ce absolute maximum rating symbol parameter condition min max unit v cc supply voltage with respect to ground -0.5 4.6 v v i dc input voltage with respect to ground -0.5 3.6 v i max dc v cc or ground current 100 ma i out dc output current, per pin -25 25 ma p d power dissipation 360 mw t stg storage temperature no bias -65 150 c t amb ambient temperature under bias -65 135 c t j junction temperature under bias 135 c
2?32 altera corporation configuration handbook, volume 2 august 2005 operating conditions table 2?15. enhanced configuration devi ce recommended operating conditions symbol parameter condition min max unit v cc supplies voltage for 3.3-v operation 3.0 3.6 v v i input voltage with respect to ground ?0.3 v cc + 0.3 v v o output voltage 0 v cc v t a operating temperature for commercial use 0 70 c for industrial use ?40 85 c t r input rise time 20 ns t f input fall time 20 ns table 2?16. enhanced configuration de vice dc operating conditions symbol parameter condition min typ max unit v cc supplies voltage to core 3.0 3.3 3.6 v v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage 0.8 v v oh 3.3-v mode high-level ttl output voltage i oh = ?4 ma 2.4 v 3.3-v mode high-level cmos output voltage i oh = ?0.1 ma v cc ? 0.2 v v ol low-level output voltage ttl i ol = ?4 ma dc 0.45 v low-level output voltage cmos i ol = ?0.1 ma dc 0.2 v i i input leakage current v i = v cc or ground ?10 10 a i oz tri-state output off-state current v o = v cc or ground ?10 10 a r conf configuration pins internal pull up ( oe , ncs , ninit , conf ) 6k table 2?17. enhanced configuration device i cc supply current values symbol parameter condition min typ max unit i cc0 current (standby) 50 100 a i cc1 v cc supply current (during configuration) 60ma 90ma a i ccw v ccw supply current (1) (1) note to table 2?17 : (1) for v ccw supply current information, refer to the appropriate flash memory data sheet at www.altera.com .
altera corporation 2?33 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet package the epc16 enhanced configuration device is available in both the 88-pin ultra fineline bga package and th e 100-pin pqfp package. the ultra fineline bga package, which is base d on 0.8-mm ball pitch, maximizes board space efficiency. a board can be laid out for this package using a single pcb layer. the epc8 and epc4 devices are available in the 100-pin pqfp package. enhanced configuration de vices support vertical migration in the 100-pin pqfp package. figure 2?8 shows the pcb routing for the 88-pin ultra fineline bga package. the gerber file for this layout is on the altera web site. table 2?18. enhanced configurati on device capacitance symbol parameter condition min max unit cin input pin capacitance 10 pf cout output pin capacitance 10 pf
2?34 altera corporation configuration handbook, volume 2 august 2005 package figure 2?8. pcb routing for 88- pin ultra fineline bga package note (1) notes to figure 2?8 : (1) if the external flash interface feature is not used, then the flash pins should be left unconnected since they are internally connected to controller unit. the on ly pins that need ex ternal connections are wp# , we# , and rp# . if the flash is being used as an external memory source, then th e flash pins should be connected as outlined in the pin descriptions section. (2) f-rp# and f-we# are pins on the flash die. c-rp# and c-we# are pins on the controller die. c-we# and f-we# should be connected together on the pcb. f-rp# and c-rp# should also be connected together on the pcb. (3) wp# (write protection pin) should be conn ected to a high level (3.3 v) to be able to program the flash bottom boot block, which is required when programming the device using the quartus ii software. package layout recommendation epc16 and epc8 enhanced configur ation devices in the 100-pin pqfp packages have different package di mensions than other altera 100-pin pqfp devices (including epc4). figure 2?9 shows the 100-pin pqfp pcb footprint specifications for enhanced configuration devices that allows for vertical migration between all three devices. these footprint dimensions are based on vendor-supplied package outline diagrams. nc oe vcc tck tdi tdo tms ncs gnd a20 a16 gnd wp# (3) nc a18 exclk a11 a8 vccw nc a17 a5 a15 a10 ninit conf tm1 a19 pgm2 a7 a4 a14 a9 pgm1 vcc dq11 porsel a6 a0 a13 dq15 dq13 a12 gnd dclk data7 nc data6 data5 dq7 dq14 pgm0 nc gnd tm0 oe# gnd ce# data0 gnd vcc a1 a2 a3 dq9 data4 data3 data2 data1 dq5 vcc dq3 dq1 dq4 vcc dq2 dq0 dq6 dq12 vcc dq10 dq8 nc vcc ry/by# c-we# f-we# f-rp# c-rp# (2) (2) (2) (2)
altera corporation 2?35 august 2005 configuration handbook, volume 2 enhanced configuration devices (epc4, epc8 & epc16) data sheet figure 2?9. enhanced configuration device pcb foot print specifications for 100-pin pqfp packages notes (1) , (2) notes to figure 2?9 : (1) used 0.5-mm increase for front and back of nominal foot length (2) used 0.3-mm increase to maximum foot width. f for package outline drawings, refer to the altera device package information data sheet . 2.4 mm 0.65-mm pad pitch 0.410 mm 0.325 mm 25.3 mm 19.3 mm 1.0 2.0 0.5 1.5 mm
2?36 altera corporation configuration handbook, volume 2 august 2005 device pin-outs device pin-outs for pin-out information, see the altera web site at www.altera.com . ordering codes table 2?19 shows the ordering codes for epc4, epc8, and epc16 enhanced config uration devices. table 2?19. enhanced configurati on device ordering codes device package temperature ordering code epc4 100-pin pqfp commercial epc4qc100 epc4 100-pin pqfp industrial epc4qi100 epc8 100-pin pqfp commercial epc8qc100 epc8 100-pin pqfp industrial EPC8QI100 epc16 100-pin pqfp commercial epc16qc100 epc16 100-pin pqfp industrial epc16qi100 epc16 88-pin ubga commercial epc16uc88

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